Silicon wafers are manufactured in sequential steps, each stage placing a pattern of material on the wafer; in this way transistors, contacts, etc., all made of different materials, are laid down. In order for the final device to function correctly, these separate patterns must be aligned correctly—for example contacts, lines and transistors must all line up. Overlay control defines the control of this pattern-to-pattern alignment. It has always played an important role in integrated circuit (IC) manufacturing, helping to monitor layer-to-layer alignment on multi-layer device structures. Misalignment of any kind can cause short circuits and connection failures, which in turn impact fab yield and profit margins. Overlay control has become even more critical now because the combination of increasing pattern density and innovative techniques, such as double patterning and immersion lithography, creates pattern-based yield challenges. Overlay metrology solutions with both higher measurement accuracy/precision and process robustness are key factors when addressing increasingly tighter overlay budgets. Higher order overlay control and in-field metrology using smaller, micro-grating or other novel targets are becoming essential for successful production ramps and higher yields.
The more semiconductor design rules shrink, it is considered that overlay error budget percentage increases compared to the product overlay budget. Even a small amount of overlay improvement is desired, but there are no conventional methods to provide overlay measurement with proper target design that is very small and easily distributed across an entirety of the chip.
A need therefore exists for methodology that provides overlay target design that can be detected and distributed across an entirety of the chip during processing of a semiconductor device.